Analog Layout Mock Interview – 2+ Years Experience

14 Views

Introduction – “Tell me about yourself”

Answer:

“Hi, I have around 5 years of experience in Analog Layout Design. I have worked on multiple projects across different technology nodes involving both analog and digital blocks.

My experience includes floorplanning, device matching, routing, shielding, power planning, EM/IR considerations, antenna fixing, and full-chip level integration.

I have handled layouts independently from schematic understanding to final signoff including DRC, LVS, ERC, antenna, and density closure.

I’m comfortable coordinating with circuit designers and can manage tasks independently while meeting project timelines.”

1. Before Starting Layout – What Inputs Are Needed?

Question

“If no schematic constraints are given, what inputs do you need before starting layout?”

Answer

Before starting layout, I clarify the following with the designer:

Circuit-Level Inputs

Critical nets
Sensitive analog nodes
Matching requirements
Current carrying paths
High-speed signals
Voltage/current specifications

Placement Constraints

Symmetry requirements
Device orientation constraints
Common centroid/interdigitation requirements
Guard ring requirements

Routing Constraints

Shielding requirements
Preferred metal layers
Analog/digital separation
Power routing strategy

Pin Information

Input/output pin locations
Top-level integration requirements

Reliability Constraints

EM limits
IR drop targets
Antenna rules
Density requirements

Technology Constraints

DRC rules
Latch-up spacing
ESD requirements

2. Schematic Changed After Layout – Buffers Added

Question

“After layout completion, designer added buffers. What will you do?”

Answer

First, I compare the updated schematic/netlist with the old version.

Steps:

Identify newly added devices
Check whether free space exists inside hierarchy
Ensure routing feasibility
Maintain symmetry/matching if nearby sensitive devices exist
Add new instances carefully
Re-route affected nets
Recheck:
- DRC
- LVS
- ERC
- Antenna
- Density

Important Interview Point

If no space exists:

Discuss with designer
Slightly expand hierarchy
Re-floorplan carefully without affecting critical matching

3. Clock vs Signal Net – Which is Critical?

Answer

Clock nets are generally more critical because:

Continuous switching activity
High frequency
Large fanout
Strong aggressor behavior

They can induce coupling noise into nearby victim nets.

Prevention Techniques

Shielding

Use grounded shield lines:
GND | CLK | GND

Increase Spacing

Reduce parasitic coupling capacitance.

Route on Higher Metals

Higher metals usually have lower resistance and less congestion.

Reduce Parallel Routing

Avoid long parallel runs near analog nets.

Orthogonal Routing

Use perpendicular routing between sensitive/aggressor nets.

4. What is Coupling Noise?

Answer

Coupling noise is unwanted noise transferred from one signal line (aggressor) to another nearby signal line (victim) through parasitic capacitance or mutual inductance.

Causes

Parallel routing
High-frequency switching
Long interconnects
Small spacing

Prevention

Shielding
Increased spacing
Shorter parallel routes
Differential routing
Proper layer selection

5. What is Matching?

Answer

Matching ensures identical electrical behavior between identical devices by minimizing layout-induced variations.

Why Matching is Important

Reduce offset
Improve accuracy
Maintain symmetry
Improve stability

Types of Matching

Interdigitation

Devices placed alternately:
ABABAB

Purpose:

Reduces local variation effects

Common Centroid

Devices arranged symmetrically around center.

Example:
ABBA

Purpose:

Cancels linear process gradients

Dummy Devices

Placed at edges.

Purpose:

Reduce edge effects
Improve environment uniformity

Guard Rings

Surround sensitive devices.

Purpose:

Reduce substrate noise
Improve isolation

6. Dummy Devices

Where Dummy Connected?

Usually:

Gate connected to source/drain
Or tied to fixed voltage depending on PDK recommendation

Half Dummy vs Full Dummy

Half Dummy

One side shared with active device.

Advantages:

Saves area

Disadvantages:

Less symmetry

Full Dummy

Complete standalone dummy device.

Advantages:

Better symmetry
Better matching

Preferred for:

High precision analog layouts

How Many Dummies?

Depends on:

Process guidelines
Matching sensitivity
Technology node

Usually:

One or more dummy rows at edges

Problem with Too Many Dummies

Increased area
Extra parasitic capacitance
Routing congestion

7. What is Body Effect?

Answer

Body effect occurs when source-to-body voltage increases, causing threshold voltage variation.

Effects

Reduced drive strength
Variation in device performance

Prevention

Proper body biasing
Proper well connections
Symmetrical layout

8. What is Substrate Noise?

Answer

Noise propagating through silicon substrate due to switching activity.

Sources

Digital switching
Clock activity
Power supply bounce

Prevention

Guard rings
Deep N-well
Separate supplies
Proper substrate contacts

9. What is Antenna Effect?

Answer

During fabrication, long floating metal accumulates charge and damages gate oxide.

Prevention Methods

Jumper Insertion

Break long metal.

Charge gets discharged through lower layers.

Reverse Bias Diode

Provides discharge path to substrate/power.

Layer Hopping

Move routing to higher layers.

10. What is Latch-Up?

Answer

Latch-up is a parasitic SCR action creating low impedance path between VDD and VSS.

Caused by parasitic PNP and NPN transistors.

Prevention

Guard Rings

Collect injected carriers.

Increase Spacing

Reduce parasitic interaction.

More Substrate/Well Contacts

Quick carrier removal.

Deep N-Well Isolation

11. LOD and STI Effects

LOD (Length of Diffusion)

Device characteristics vary due to diffusion spacing.

Prevention

Symmetrical diffusion
Use dummies
Equal spacing

STI Effect

Stress from shallow trench isolation changes transistor behavior.

Prevention

Keep identical surroundings
Use dummy devices
Symmetrical placement

12. Explain PMOS & NMOS Layers

NMOS Structure

P-substrate
N+ source/drain
Poly gate
Contact
Metal
Well taps

Function

Conducts when gate is high.

PMOS Structure

N-well
P+ source/drain
Poly gate
Contacts
Metals

Function

Conducts when gate is low.

13. What if VDD Connected to GND?

Answer

Direct short circuit between supplies.

Effects

Huge current flow
Chip damage
EM issues
Possible latch-up

Detected during:

LVS/ERC
Short checks

14. Analog vs Digital Layout Challenges

Analog Challenges

Matching
Noise sensitivity
Symmetry
Parasitics

Digital Challenges

Congestion
Timing
Power routing
Density

How to Handle Both?

Separate analog/digital regions
Shield critical analog nets
Use guard rings
Dedicated supplies

Do You Shield Digital Signals?

Not all.

Usually shield:

Clock nets
High-speed buses
Critical timing nets

15. EM & IR Drop

EM (Electromigration)

Metal damage due to excessive current density.

Prevention

Wider metals
More vias
Current distribution

IR Drop

Voltage drop due to metal resistance.

Prevention

Strong power grid
Wider metals
More straps

Which Fixed First?

Usually EM first because metal reliability failure is permanent.

Metal Width Calculation

Based on:
$\frac{I}{A}$

Where:

J = current density
I = current
A = metal area

From PDK current density limits:
Calculate required metal width.

16. Metal Density

Answer

Foundries require uniform metal distribution for CMP process.

Low density causes:

Dishing
Erosion
Thickness variation

Fixes

Add dummy metal fill
Maintain spacing rules
Avoid affecting sensitive analog areas

17. ERC Errors

Common ERC Issues

Floating nets
Missing well taps
Supply shorts
Unconnected bulk
Gate oxide stress

Fixing Method

Analyze ERC report
Identify violation location
Verify schematic intent
Correct connectivity/layout
Re-run verification