Analog Layout Engineer Interview Questions | RC Matching & Routing Compensation
- If you have four inverter standard cells (A, B, C, D) that are intended to behave as matched pairs, but the physical spacing ended up different:
- A–B spacing = 5 µm
- C–D spacing = 10 µm
As a layout engineer:
- What issues can arise due to this mismatch?
- How would you analyze the impact?
- What techniques would you use to achieve RC matching without changing placement?
Step 1: Identify Potential Issues
- Since both placement and routing are unmatched, the following issues may occur:
Parasitic Resistance Mismatch
- Different routing lengths create different wire resistance.
- Causes delay mismatch between the inverter pairs.
Parasitic Capacitance Mismatch
- Different spacing and routing environments lead to different coupling capacitances.
- Creates unequal transition times and propagation delays.
Coupling Noise
- One pair may experience higher aggressor coupling than the other.
- Can introduce jitter or timing variation.
Since placement is fixed, I would focus on layout RC matching through routing optimization.
I will Implement symmetric serpentine routing using preferred metal directions, ensuring both paths have identical wire length, via count and routing environment( No metal/fill overlap)
Since A–B are separated by 5 µm and C–D by 10 µm, I would use the longer-distance pair (C–D) as the reference and add routing to the shorter pair (A–B)
so that the effective routing length for both pairs is equivalent to 10 µm. This helps achieve comparable RC characteristics and maintain electrical matching between A–B and C–D.
